Home > Workshops >

Signal Processing with FPGA, Python & no RTL Design!

Adam Taylor - Available in 12 days, 18 hours and 37 minutes (2021-10-06 08:00 EDT)

To take full advantage of this workshop, you'll need an Arty Z7 board.  If you decide to purchase one, make sure to: 

  1. Select the Z7-20 version.
  2. Enter the promo code DSPARTYZ725 to save 25%

Developing programmable logic solutions is moving up the levels of abstraction.

In this session we will use the Arty Z7 board and the Xilinx PYNQ framework to accelerate signal processing algorithms (FFT, FIR Filters) in programmable logic using with a combination of Python and High-Level Synthesis (C/C++). Techniques such as this will allow us to leverage the processing capabilities of programmable logic without the requirement to develop solutions using traditional FPGA Register Transfer Languages. This enables smaller, more power-efficient solutions.

This session will introduce the PYNQ framework and explain how it interacts with the programmable logic. We will then explore how we can use HLS – what is it, how do we go from untimed C to logic gates and what optimisations do we need. Finally, we will look at how we can build PYNQ overlays using IP Integrator which can be loaded onto the Arty Z7 for use with our Python application using Jupyter Notebooks / Labs. 

M↓ MARKDOWN HELP
italicssurround text with
*asterisks*
boldsurround text with
**two asterisks**
hyperlink
[hyperlink](https://example.com)
or just a bare URL
code
surround text with
`backticks`
strikethroughsurround text with
~~two tilde characters~~
quote
prefix with
>

No comments or questions yet. Will you be the one who will break the ice?